1. Field of the Disclosure
This specification relates to a Liquid Crystal Display (LCD) device, and particularly, to an LCD device having a varied structure of a drain electrode and a fabricating method thereof.
2. Background
In general, the driving principle of a liquid crystal display (LCD) device uses an optical anisotropy and polarization properties of liquid crystal. Liquid crystals have a thin, long structure, so they have orientation in an alignment of molecules, and the direction of the alignment of molecules can be controlled by intentionally applying an electric field to the liquid crystal.
Thus, when the direction of the alignment of molecules of the liquid crystal is adjusted, the alignment of molecules of the liquid crystal can be changed, and light is refracted in the direction of the molecular alignment of the liquid crystal by optical anisotropy, thus displaying image information.
Currently, an active matrix liquid crystal display (AM-LCD) (which will be referred to as an ‘LCD’, hereinafter) in which thin film transistors (TFTs) and pixel electrodes connected to the TFTs are arranged in a matrix form has come to prominence because of its excellent resolution and video implementation capabilities.
The LCD includes a color filter substrate (i.e., an upper substrate) on which common electrodes are formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and liquid crystal filled between the upper substrate and the lower substrate. In the LCD, the common electrode and the pixel electrodes drive liquid crystals by an electric field applied vertically, having excellent characteristics of transmittance, aperture ratio, and the like.
However, the driving of liquid crystals by the electric field applied vertically is disadvantageous in that viewing angle characteristics are not good. Thus, in order to overcome the shortcomings, a method for driving liquid crystal by in-plane switching has been newly proposed. The method for driving liquid crystal by the in-plane switching has excellent viewing angle characteristics.
Although not shown, in the in-plane switching mode LCD is configured such that a color filter substrate and an array substrate face each other, and a liquid crystal is interposed therebetween.
On the array substrate, a TFT, a common electrode, and a pixel electrode are formed on each of a plurality of pixels defined on the TFT substrate. Here, the common electrode and the pixel electrode are spaced apart from each other in parallel on the same substrate.
The color filter substrate includes black matrixes at portions, which correspond to gate lines and data lines formed on the TFT substrate, and the TFTs formed on intersecting points between the data and gate lines, and color filters corresponding to the pixels.
The liquid crystal layer is driven by a horizontal electric field of the common electrode and the pixel electrode.
In the in-plane switching mode LCD device configured as described above, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure luminance.
A Fringe Field Switching (FFS) technique has been proposed to maximize the luminance improvement effect. The FFS technique precisely controls liquid crystal to eliminate a color shift and obtain high contract ratio, implementing high screen quality compared with the general in-plane switching technique.
Also, as a structure for preventing a reduction of transmittance, a Dual Rate Driving (DRD) structure employing the FFS mode has been currently proposed. This structure is a structure in which a conventional gate common line formed in a horizontal direction is removed and a common line is formed vertical to the gate line by using a metal layer for forming a data line.
An open area which is not covered by a black matrix (BM) is designed equally on left and right pixels based on a data line, preventing a perceptual error generated by a luminance difference between the left and right pixels due to shifting of the black matrix.
In addition, when overlapping portions between metal layers for forming the gate line and the data line are shifted due to process variation, storage capacitor (Cgs) values of the left and right pixels are different from each other. The left and right pixels thereby exhibit different luminance from each other, causing a perceptual error. To overcome such defect, a technique of forming a parasitic capacitor (Cgs) compensation pattern on each gate line has been proposed.
From this perspective, a DRD type LCD device employing the conventional FFS mode will be described with reference to FIGS. 1 and 2.
FIG. 1 is a planar view of an FFS type LCD device according to the related art.
FIG. 2 is a sectional view taken along the line II-II of FIG. 1, which shows the FFS type LCD device according to the related art.
An FFS type LCD device according to the related art, as shown in FIGS. 1 and 2, includes a first substrate 11 and a second substrate 31 bonded to each other with a spaced distance therebetween; a plurality of gate lines 15A and 15B aligned on the first substrate 11 in one direction in parallel to each other; a gate electrode 15a extending from each of the gate lines 15A and 15B; a gate insulating layer 17 formed on an entire surface of the substrate having the gate electrode 15a; a data line 23 and a common line 23d formed on the gate insulating layer 17 to define pixel regions at perpendicularly intersecting points with the gate lines 15A and 15B; a large pixel electrode 13 disposed on the pixel region defined at the intersecting point between each of the gate lines 15A and 15B and the data line 23 and the common line 23d; a Thin Film Transistor (TFT) T disposed at the intersecting point between each of the gate lines 15A and 15B and the data line 23, and having an active layer 19 disposed on the gate electrode 15a and the gate insulating layer 17, an Ohmic contact layer 21 on the active layer 19, and a source electrode 23a and a drain electrode 23b spaced apart from each other; a protrusion pattern 23c formed on the gate line 15B of the gate lines 15A and 15B; a passivation layer 25 formed on an entire surface of the first substrate 11 having the protrusion pattern 23c, and exposing the pixel electrode 13; a plurality of branched common electrodes 29a formed on the passivation layer 25 to be connected to the common line 23d and overlap the pixel electrode 13a; a pixel electrode connection pattern 29b to connect the pixel electrode 13 to the drain electrode 23b via the exposed passivation layer 29b; a black matrix 33 formed on the second substrate 31; a color filter layer 35 located between the black matrixes 33; a column spacer 37 formed on the second substrate 31 corresponding to the protrusion pattern 23c so as to contact the protrusion pattern 23c; and a liquid crystal layer 41 disposed between the first substrate 11 and the second substrate 31.
The protrusion pattern 23c is formed on the gate line 15A or the adjacent gate line 15B to overcome touch and gravity influences generated by a contact area between the TFT and the column spacer 37 formed on the second substrate 31.
FIG. 3 is an enlarged planar view of a TFT unit, corresponding to a part “A” in FIG. 1, which schematically shows the protrusion pattern, which is formed on the gate line to be adjacent to the straight drain electrode, and the black matrix.
Especially, FIG. 3 shows a case where a black matrix 33a having a first area A1 overlaps a non-pixel region to maintain the existing open area as it is, namely, a case where the protrusion patter 23c is formed on the gate line 15A.
Here, since the protrusion pattern 23c is formed as the same metal layer as the drain electrode 23b, the protrusion pattern 23c and the drain electrode 23b are disposed with an extremely narrow distance d1 therebetween, which is shorter than about 0.7 μm.
As the protrusion pattern 23c and the drain electrode 23b formed of the same metal layer are disposed with the extremely narrow distance d1, it is highly likely to cause the protrusion pattern 23c and the drain electrode 23b to be shorted from each other.
FIG. 4 is an enlarged planar view of the TFT unit, corresponding to the part “A” in FIG. 1, which schematically shows the protrusion pattern formed on the lower gate line and the black matrix.
Especially, FIG. 4 shows that the protrusion pattern 23c is formed on the lower gate line 15B, other than on the upper gate line 15A, to prevent the protrusion pattern 23c and the drain electrode 23b from being shorted from each other.
Here, as the protrusion pattern 23c is formed on the lower gate line 15B, a distance between the protrusion pattern 23c and the drain electrode 23b increases. This may eliminate the concern about the occurrence of the shortcircuit between the protrusion pattern 23c and the drain electrode 23b. 
However, with the protrusion pattern 23c being formed on the lower gate line 15B, the column spacer 37 may cause a defect when it is located in correspondence with the lower gate line 15B. To avoid this, a black matrix 33b is designed to have a second area A2 larger by a width W1 than the first area A1.
Therefore, the black matrix 33b has to be formed wider than in FIG. 3. Accordingly, the black matrix 33b is disposed to overlap even a part of the open area of the pixel, thereby reducing the open area of the pixel by the overlapped part.
As mentioned above, according to the related art FFS type LCD device structure, as the protrusion pattern is formed on the lower gate line 15B to prevent the protrusion pattern and the drain electrode 23b from being shorted from each other, a defect may be caused due to the column spacer 37 when the column spacer 37 is located in correspondence with the lower gate line 15B. This may make the black matrix formed wider to overlap a part of the open area including a non-open area, reducing the open area of the pixel.